I am a postdoctoral associate working in the Systems Software Research Group (SSRG) led by Prof. Binoy Ravindran at Virginia Tech. I was an assistant professor at Alexandria University, Faculty of Engineering before moving to Virginia Tech.
I obtained my PhD in July of 2015 from Virginia Tech under supervision of Prof. Binoy Ravindran. The title of my dissertation is "On Optimizing Transactional Memory: Transaction Splitting, Scheduling, Fine-grained Fallback, and NUMA Optimization".
- Transactional Memory
- Concurrency Control
- Parallel Programming
- Distributed Computing
- Managing Resource Limitation of Best-Effort HTM, M. Mohamedin, R. Palmieri, A. Hassan, and B. Ravindran, IEEE Transactions on Parallel and Distributed Systems (IEEE TPDS), 2016
- On Designing NUMA-Aware Concurrency Control for Scalable Transactional Memory, M. Mohamedin, R. Palmieri, S. Peluso, and B. Ravindran, ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2016), Poster paper, March 12-16, 2016, Barcelona, Spain
- Brief Announcement: On Scheduling Best-Effort HTM Transactions, M. Mohamedin, R. Palmieri and B. Ravindran, 27th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA), June 2015, Portland, Oregon, USA
- ByteSTM: Virtual Machine-level Java Software Transactional Memory, M. Mohamedin, B. Ravindran, and R. Palmieri, 15th International Conference on Coordination Models and Languages (COORDINATION 2013), June 2013, Firenze, Italy
- HydraVM: Extracting Parallelism from Legacy Sequential Code Using STM, M. Saad, M. Mohamedin, and B. Ravindran, 4th USENIX Workshop on Hot Topics in Parallelism (HotPar 2012), June 2012